On Synthesis of Reduced Order Models
نویسندگان
چکیده
Several synthesis procedures for realizing reduced mathematical models into RLC circuits are presented. The approaches are compared in terms of: quality of approximation , preservation of structure and sparsity and applicability to Multi-Input-Multi-Output systems. 1. Introduction. An emerging problem in simulation of VLSI circuits is that of model reduction for the interconnect. Advanced passivity preserving reduction methods have been developed, which reduce the dynamical system of an original circuit to an approximate mathematical model of smaller dimension. Passivity ensures that the reduced mathematical model can be synthesized into an RLC netlist [1], which is used in place of the original circuit during simulation. This survey compares several synthesis methods for realizing reduced SISO and MIMO systems into RLC circuits.
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